Article ID: 000092261 Content Type: Troubleshooting Last Reviewed: 09/22/2022

Why is there a Minimum Pulse Width violation when using a dedicated Intel® Stratix® 10 or Intel® Agilex™ FPGA REFCLK_GXB pin to clock the refclk of an IOPLL?

Environment

  • Intel® Quartus® Prime Pro Edition
  • IOPLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you might see a Minimum Pulse Width violation on your pll refclk pin when using a dedicated REFCLK_GXB pin to clock the refclk of an IOPLL.

    The target for the Minimum Pulse Width violation will typically be to add <refclk pin name>~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c0_div

    Resolution

    To avoid the error, add the following Synopsys* Design Constraints File (.sdc) constraint:

    disable_min_pulse_width [get_cells <refclk pin name>~inputFITTER_INSERTED_FITTER_INSERTED]

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Agilex™ 7 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.