Why is there a Minimum Pulse Width violation when using a dedicated Intel® Stratix® 10 or Intel Agilex® 7 FPGA devices REFCLK_GXB pin to clock the refclk of an IOPLL?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you may see a Minimum Pulse Width violation on your pll refclk pin when using a dedicated REFCLK_GXB pin to clock the refclk of an IOPLL.

The target for the Minimum Pulse Width violation will typically be to <refclk pin name>~inputFITTER_INSERTED_FITTER_INSERTED~fpll_c0_div

To avoid the error, add the following Synopsys* Design Constraints File (.sdc) constraint:

disable_min_pulse_width [get_cells <refclk pin name>~inputFITTER_INSERTED_FITTER_INSERTED]