Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see negative-edge clocks being reported as positive-edge clocks by Timing Analyzer for registers in IO Cells. This problem only affects designs targetting Intel® Agilex™ devices.
To work around this problem, manually disable register packing on any FF that has an inverted clock in an IO Cell. For example:
set_instance_assignment -name FAST_INPUT_REGISTER -to <to> -entity <entity name> OFF
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER -to <to> -entity <entity name> OFF
set_instance_assignment -name FAST_OUTPUT_REGISTER -to <to> -entity <entity name> OFF
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.