Article ID: 000092062 Content Type: Troubleshooting Last Reviewed: 10/18/2022

Why does the performance degrade in Partial Reconfiguration implementation revision when compared with the base revision?

Environment

  • Intel® Quartus® Prime Design Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see performance degradation in Partial Reconfiguration (PR) implementation revision when compared with the base revision because in the PR implementation revision the placement and routing are fixed in the static region. This affects the flexibility of placement and routing in the PR region.

    Resolution

    To reduce the performance degradation in PR implementation revision, follow these steps:

    1. Ensure that the periphery resources are placed close to the associated logic.
    2. Minimize the number of signals between periphery resources crossing the PR region.
    3. For the remaining signals:
      • Add enough pipelining registers.
      • Create a floor plan for the interconnection logic crossing PR region so that it runs along the PR region boundary like a channel.
    4. Lock down the PR boundary port wire-LUT (suffix ~IPORT/~OPORT) on the side of PR region that connects to the static region. Also ensure it is close to the boundary of the PR region.

    Related Products

    This article applies to 4 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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