Article ID: 000091946 Content Type: Troubleshooting Last Reviewed: 08/24/2022

Why is the Intel® Stratix® 10 L-tile and H-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example missing two setup clocks in the Timing Analyzer Setup Summary?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the following clocks are missing in the setup summary when compiling the L-tile and H-tile Avalon® Streaming Intel® FPGA IP for PCI Express* for Intel® Stratix® 10 FPGA devices.

    • dut|dut|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|xcvr_hip_native|ch0
    • dut|dut|altera_avst512_iopll|altera_ep_g3x16_avst512_io_pll_s10_outclk0

     

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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