Why doesn’t my link come up when I use a 400G optical module in my Intel Agilex® 7 FPGA I-Series F-tile design?

For the Intel Agilex® 7 FPGA F-Tile FGT transceiver above 50G PAM4 design, for the adaptation to be successful when using 400G optical modules for loopback, you need to set the media mode to VSR/Optics. 

To work around this problem, refer to the set_media_mode process in the following .tcl file: 

ttk_helper_fgt_eth.tcl

To set the media mode to VSR/Optics, follow these steps:

1. For logical channels 0 to 15, 0xFFFFC[1:0] return value indicates logical channel 0's physical location. If the return value is 2'b00, it means logical channel 0 is located in physical lane 0. 2'b01 means logical channel 0 is located in physical lane 1, 2'b10 means physical lane 2, and 2'b11 means physical lane 3. This return value applies to all 16 logical channels. 
2. 0x1FFFFC[1:0] return value indicates logical channel 1's physical location.
   0x2FFFFC[1:0] return value indicates logical channel 2's physical location.
   ...
   0x8FFFFC[1:0] return value indicates logical channel 8's physical location. 
3. For Ch0 ~ Ch3, follow these steps:
      a) Write 0x14a(lane_number)64 to address 0x9003C.
      b) Poll address 0x90040 until bit 14 = 0 and bit 15 = 1.
      c)  Write 0x142(lane_number)64 to address 0x9003C.
      d) Poll address 0x90040 until bit 14 = 0 and bit 15 = 0.
   
   If you want to switch back to default, follow these steps：
      a) Write 0x10a(lane_number)64 to address 0x9003C
      b) Poll address 0x90040 until bit 14 = 0 and bit 15 = 1.
      c) Write 0x102(lane_number)64 to address 0x9003C.
      d) Poll address 0x90040 until bit 14 = 0 and bit 15 = 0.
4. For Ch4 ~ Ch7, follow these steps:
      a) Write 0x14a(lane_number)64 to address 0x49003C.
      b) Poll address 0x490040 until bit 14 = 0 and bit 15 = 0.
      c) Write 0x142(lane_number)64 to address 0x49003C.
      d) Poll address 0x490040 until bit 14 = 0 and bit 15 = 1.
   
   If you want to switch back to default, follow these steps: 
      a) Write 0x10a(lane_number)64 to address 0x49003C.
      b) Poll address 0x490040 until bit 14 = 0 and bit 15 = 1.
      c) Write 0x102(lane_number)64 to address 0x49003C.
      d) Poll address 0x490040 until bit 14 = 0 and bit 15 = 0.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.