Article ID: 000091590 Content Type: Error Messages Last Reviewed: 07/19/2022

Why does the ModelSim*-Intel® FPGA software simulator generates an error while simulating the Intel® Agilex™ FPGA EMIF IP design example with Efficiency monitor enabled ?

Environment

  • Intel® Quartus® Prime Design Software
  • Intel® FPGA Simulation Tools
  • External Memory Interfaces Debug Component Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    While running the register transfer level (RTL) simulation for the Intel® Agilex™ FPGA EMIF IP design example with Efficiency monitor enabled, errors occur with the following error message: 

    Error (vsim-8604)   ../ip/ed_sim/ed_sim_dut/altera_amm_effmon_191/sim/altera_amm_effmon_single_top.sv(246): NaN (not a number) resulted from a division operation 

    Resolution

    This issue has been fixed in the Intel® Quartus® Prime Pro Edition Software version 21.2 or later versions.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® FPGA Configuration Devices

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