When the HPS F2H interface is configured as ACE-lite and connected to an ACE-lite master (for example, from cache coherency translator IP or custom ACP adapter IP) in Intel® Stratix® 10 SX devices or Intel® Agilex® SX devices, you may see below error when you generate the design in Platform Designer tool:
Error: Interconnect is required but is currently not supported for acelite interface type.
The error was only reported by Intel® Quartus® Prime Pro Edition Software versions 22.1 and later.
Currently, the Platform Design tool does not add any adapter between ACE-lite master-slave pair to help the connection work correctly. Platform Design tool in Quartus version 22.1 starts to check ACE-lite connection and would report errors if any signal mismatch is found between ACE-lite connection. Designers must check all signals, for example, ARID, AWID, BID, RID, ARUSER, AWUSER, etc. to make sure the ACE-lite connection work as expected.
When the HPS F2H ACE-lite interface is used, the width of ARID, AWID, BID, and RID from the ACE-lite master should be set as 5 to match exactly the HPS F2H ACE-lite interface. ARUSER and AWUSER signals are also needed to be exactly matched between the ACE-lite connections.