Article ID: 000091381 Content Type: Troubleshooting Last Reviewed: 07/14/2022

Why do I see unexpected result when using Configuration Intercept Interface (CII) to access configuration space register with address greater than 8 bits on the P-Tile or F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Wharf Rock Avalon-ST for PCI Express
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.1 and earlier version, configuration space register access using Configuration Intercept Interface (CII) with address greater than 8 bits may not work correctly when VIRTIO support is enabled. Configuration space register access where the lower 8 bits of the register address coincide with VIRTIO register will be recognized as VIRTIO register access regardless of the upper two address bits value.

    Resolution

    This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software v22.2.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 DX FPGA

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