Article ID: 000090990 Content Type: Error Messages Last Reviewed: 01/11/2023

When using the Intel® Agilex™ FPGA P-Tile, why are simulation errors seen when compiling the Multi Channel DMA Intel® FPGA IP for PCI Express testbench in the Cadence Xcelium simulator?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    As stated in Table 34. Supported Simulators for MCDMA IP P-Tile of the Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide, the Cadence Xcelium simulator is not supported, if simulation of this IP configuration is attempted using Cadence Xcelium, the following error will be seen:

    $>./xcelium_setup.sh
    ~~~~~
    xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
    xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
    xmsim: 20.03-s005: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
    xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries.

    Resolution

    Support for the Cadence Xcelium simulator of this IP configuration is planned for a future release of the Intel® Quartus® Prime Pro Edition Software.

    To work around this problem with the existing IP release, please ensure a supported simulator is used.

    Related Products

    This article applies to 3 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Agilex™ F-Series Development Kit DK-DEV-AGF014E2ES
    Intel® Agilex™ F-Series Development Kit DK-DEV-AGF014EA

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