Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example may fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled.

To work around this problem in the Intel® Quartus® Prime Pro Software version 22.1 and earlier, launch the Design Space Explorer II in the Intel® Quartus® Prime Pro Software and perform seed sweeps.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.