Critical Issue
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you may see failures in hardware when the warning message below is displayed during the 'Analysis & Synthesis' stage. Affected designs will have a mismatch between RTL and synthesized netlist.
The designs impacted by the synthesis problem will see the following warning in the synthesis report file (*.syn.rpt).
Warning (13228): Verilog HDL or VHDL warning at <file>: defparam under generate scope cannot change parameter values outside of its hierarchy File: <file>
A patch is available to work around this problem for the Intel® Quartus® Prime Pro Edition Software version 22.1. Download and install patch 0.05 from the appropriate link below.
- Download patch Intel® Quartus® Prime Pro Edition 22.1 Patch 0.05 for Windows (.exe)
- Download patch Intel® Quartus® Prime Pro Edition 22.1 Patch 0.05 for Linux (.run)
- Download the Readme for Intel® Quartus® Prime Pro Edition 22.1 Patch 0.05 (.txt)
This problem is fixed in all future releases of the Intel® Quartus® Prime Pro Edition Software starting from 22.1.