Due to a problem in the Ethernet Toolkit software, when you intantiate a 100G-2 PAM4 in E-tile Hard IP for Ethernet Intel® FPGA IP on Intel® Agilex™ FPGA and observe uncorrected codewords in the Intel® Agilex™ E-tile Hard IP Ethernet Toolkit GUI, the count value will always be 0.
The correct value can be read from the forward error correction (FEC) register 0x220.
This issue is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.