Article ID: 000090429 Content Type: Troubleshooting Last Reviewed: 01/10/2023

Why do I see uncorrectable errors on PCI Express link when running the P-Tile Debug Toolkit’s Eye Viewer margining feature ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express Eye Viewer feature of the P-Tile Debug Toolkit does not support independent error sampler for performing eye margining.
    The eye margining is performed on the actual data path. As a result, the eye margining may produce uncorrectable errors in the data stream and cause the LTSSM to go to the Recovery state
     

    Resolution

    To work around this problem, mask out all errors (e.g. AER registers) while performing the eye margining and reset all error counters
    error registers, and so on after the eye margining completes.
     

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 DX FPGA

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