The following errors may be seen in the Quartus® Prime Pro Edition Software version 21.3 when you simulate a 1-bit wide, single-clock FIFO FPGA IP generated in VHDL.
# ** Error: /nfs/site/disks/psg_data_30/scabanda/ips_cases/690706/adci_rd_error_fifo_auto/sim/adci_rd_error_fifo_auto.vhd(34): (vcom-1133) Type mismatch found on port "data".
# In the component "adci_rd_error_fifo_auto_fifo_1910_5xd5sry_cmp", the port type is "ieee.std_logic_1164.STD_LOGIC".
# In the entity "adci_rd_error_fifo_auto_fifo_1910_5xd5sry", the port type is "ieee.std_logic_1164.STD_LOGIC_VECTOR"
# ** Error: /nfs/site/disks/psg_data_30/scabanda/ips_cases/690706/adci_rd_error_fifo_auto/sim/adci_rd_error_fifo_auto.vhd(34): (vcom-1133) Type mismatch found on port "q".
# In the component "adci_rd_error_fifo_auto_fifo_1910_5xd5sry_cmp", the port type is "ieee.std_logic_1164.STD_LOGIC".
# In the entity "adci_rd_error_fifo_auto_fifo_1910_5xd5sry", the port type is "ieee.std_logic_1164.STD_LOGIC_VECTOR"
To work around this problem in the Quartus® Prime Pro Edition Software version 21.3, generate the 1-bit wide, single-clock FIFO FPGA IP in Verilog and create a VHDL wrapper. Connect the VHDL wrapper to the main design.
This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.