Article ID: 000089766 Content Type: Troubleshooting Last Reviewed: 04/06/2022

Why is there no response in AXI read data channel in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP simulation?

Environment

  • Intel® Quartus® Prime Design Software
  • High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When the signals in HBM2 AXI interface are set to unknown status before and after the read command in HBM2 simulation, you might see that there is no response in HBM2 AXI read data channel.

    Resolution

    Because there is no unkown status in actual hardware behavior, the signals in AXI interface will be captured as either 0 or 1, so the unknown status in simulation are not expected.

    To work around this, you can set the signlas in HBM2 AXI interface in simulation to random values instead of setting them to unknown status.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA

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