How can I reduce the Partial Reconfiguration (PR) bitstream file size in the Intel® Stratix® 10 and Intel Agilex® FPGA devices?

The size of the PR bitstream file for the Intel® Stratix® 10 and Intel Agilex® FPGA devices is dependent on the number of clock sectors covered by the PR region. A larger number of clock sectors covered by the PR region results in a larger bitstream file size. Consequently, PR programming time will increase accordingly.

To reduce PR bitstream file size, follow the two tips below:

1. Target only the necessary number of clock sectors for PR region.
2. When aligning the Routing Region to clock sectors, ensure that the Routing Region is one LAB row/column inset from the edge of clock sector boundaries.