Article ID: 000088999 Content Type: Compatibility Last Reviewed: 12/31/2021

How to set HPS SDRAM PLL reference clock resource for Cyclone® V SoC device?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Intel® SoC FPGA Embedded Development Suite Standard Edition
  • Arria® V Cyclone® V Hard Processor System Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In Cyclone® V SoC device, there are three clock sources for hard processor system (HPS) SDRAM phase-locked loop (PLL) named eosc1_clkeosc2_clk and f2s_sdram_ref_clk, but it's not available to specify the clock source in HPS intellectual property (IP) GUI. 

    Resolution

    The selection of clock source for HPS SDRAM PLL is controlled by Preloader software:

    1. Generate spl_bsp from handoff files, and pll_config.h is generated in the "generated" folder of BSP target directory.

    2. In the pll_config.h file, change the following value to the expected clock resource:

    #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) 

    The value 0 means to use eosc1_clk as SDRAM PLL reference clock source, 1 means to use eosc2_clk and 2 means to use f2s_sdram_ref_clk.

    3. Compile the Preloader and build the Preloader image.

    Related Products

    This article applies to 3 products

    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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