Article ID: 000088800 Content Type: Troubleshooting Last Reviewed: 12/15/2021

Why does compilation fail in the Fitter stage for designs that contain the Multi Channel DMA Intel® FPGA IP for PCI Express?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Designs that contain the Multi Channel DMA Intel® FPGA IP for PCI Express will fail in the Fitter stage of compilation if the Enable PIPE PHY Interface option is not checked in the MCDMA Settings tab of the IP parameter window.

    Resolution

    Ensure the Enable PIPE PHY Interface option is selected in the MCDMA Settings tab of the Multi Channel DMA Intel® FPGA IP for PCI Express parameter window.

     

    This problem is scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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