Article ID: 000088714 Content Type: Error Messages Last Reviewed: 01/30/2023

Why does the Intel® Agilex™ 7 F-Tile SDI II FPGA IP design example fail to compile at the Support-Logic Generation stage?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4, the Intel® Agilex™ 7 F-Tile SDI II FPGA IP design example will fail at the Support-Logic Generation stage during compilation with the following error message:

    Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.4. 

    Download and install Patch 0.01 from the following links:

    This problem is being fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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