Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, you may see this internal error when compiling designs that target Intel Agilex® devices and include the LVDS SERDES Intel FPGA IP core. The error occurs when one I/O bank has several LVDS SERDES Intel FPGA IP cores with different reset signals connected to the Clock Phase Alignment (CPA) block.
Resolution
To work around this problem, use one reset signal for all CPA blocks within the same I/O bank.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.