Article ID: 000088304 Content Type: Error Messages Last Reviewed: 11/24/2021

Internal Error: Sub-system: AMM, File: /quartus/db/amm/amm_atom_mod_util_impl.cpp, Line: 4631

Environment

  • Intel® Quartus® Prime Pro Edition
  • LVDS SERDES Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, you may see this internal error when compiling designs that target Intel® Agilex™ devices and include the LVDS SERDES Intel FPGA IP core. The error occurs when one I/O bank has several LVDS SERDES Intel FPGA IP cores which have different reset signals connected to the Clock Phase Alignment (CPA) block.

    Resolution

    To work around this problem, use one reset signal for all CPA blocks within the same I/O bank.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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