Due to the auto-adjust frequency feature of the Intel® FPGA Download Cable II (formerly referred to as the USB Blaster II download cable), the frequency (TCK) is set to 24 MHz after every power cycle, but the Intel Agilex® DDR4 FPGA IP example design constraints the JTAG frequency (TCK) to 16 MHz causing the In-System Sources and Probes instance to capture incorrect data.
To work around this problem, set JTAG TCK to 16 MHz before running the Intel Agilex® FPGA DDR4 IP example design test. Once the frequency has been set correctly, you can safely ignore the following warning when compiling your design:
Warning: The External Memory Interface IP Example Design is using default JTAG timing constraints from jtag_example.sdc. For correct hardware behavior, you must review the timing constraints and ensure they accurately reflect your JTAG topology and clock speed.