Article ID: 000088223 Content Type: Troubleshooting Last Reviewed: 04/18/2022

Why does the In-System Sources and Probes instance shows incorrect waveform behavior when using the Intel® Agilex™ FPGA DDR4 IP example design?

Environment

  • Intel® Quartus® Prime Pro Edition
  • In-System Sources & Probes Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to the auto-adjust frequency feature of the Intel® FPGA Download Cable II (formerly referred to as the USB Blaster II download cable) the frequency (TCK) is set to 24 MHz after every power cycle but the Intel® Agilex™ DDR4 FPGA IP example design constraints the JTAG frequency (TCK) to 16 MHz causing the In-System Sources and Probes instance to capture incorrect data.

     

    Resolution

    To work around this problem, set JTAG TCK to 16 MHz before running the Intel® Agilex™ FPGA DDR4 IP example design test. Once the frequency has been set correctly, you can safely ignore the following warning when compiling your design:

    Warning: The External Memory Interface IP Example Design is using default JTAG timing constraints from jtag_example.sdc. For correct hardware behavior, you must review the timing constraints and ensure they accurately reflect your JTAG topology and clock speed.

     

     

    Related Products

    This article applies to 2 products

    Intel® FPGA Download Cable II driver
    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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