Why do I see unexpected behavior on dedicated HPS IOs for my Agilex™ 7 SoC FPGA design, and incorrect pin locations in the pinout report?

Due to a problem in the Quartus® Prime Pro Edition Software version 21.1 and later, dedicated HPS output pins may be incorrectly mapped to pin locations during the Fitter stage.

This might cause a mismatch between the pin locations defined in the HPS IP parameter GUI in Platform Designer and the .pinout file generated during compilation and unexpected behavior at runtime. 

To avoid or work around this problem, do either of the following : 

• Add pin location assignments to the HPS output pins in the .qsf file according to the HPS IP parameter GUI in Platform Designer  OR
• Use the Assignment Editor in Quartus® Prime Pro Edition Software to force the Fitter to place HPS outputs in designated pin locations. 

This problem is fixed in Quartus® Prime Pro Edition Software version 22.2.