Article ID: 000087360 Content Type: Troubleshooting Last Reviewed: 07/09/2018

Why does the Intel® Stratix® 10 PCIe* IP core infer a latch when used in root port mode?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Intel® Stratix® 10 PCIe* IP core in root port mode, the following inferred latch warning will be reported during analysis and synthesis:

    Warning (13228): Verilog HDL or VHDL warning at altera_pcie_s10_rp_reg.sv(368): latch inferred for net eop_cycles[3]

    This problem has been confirmed as a bug.

    Resolution

    No workaround for this problem exists.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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