Description
When using the Stratix® 10 PCIe* IP core in root port mode, the following inferred latch warning will be reported during analysis and synthesis:
Warning (13228): Verilog HDL or VHDL warning at altera_pcie_s10_rp_reg.sv(368): latch inferred for net eop_cycles[3]
This problem has been confirmed as a bug.
Resolution
No workaround for this problem exists.
This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 18.1