Article ID: 000087348 Content Type: Error Messages Last Reviewed: 08/07/2017

Error (18496): Output is too close to PLL clock input pin

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this error message when compiling a design targetting a MAX® 10 device with no pin assignment in the Quartus® Prime software version 16.1.

 

Resolution

To work around this issue, manually assign the location of the affected pin away from a PLL clock input pin in Assignment Editor.

This issue is fixed in Quartus Prime version 17.0.

Related Products

This article applies to 1 products

Intel® MAX® 10 FPGAs

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