Quartus® II synthesis may generate the above warning when compiling a VHDL source file that declares a register signal of type integer. In particular, if you do not assign an inital value when declaring the signal, Quartus II synthesis assumes the left end of the integer range is the power-up value for the register. If your code later applies an asynchronous reset value to this register which does not equal the assumed power-up level, Quartus II synthesis uses the reset value as the power-up value instead and generates the above warning message.
For example if your code declares a signal like this:
signal count_down : integer range 0 to 255;and later applies a reset value like this:
process (clk, reset)
begin
if reset = '1' then
count_down <= 255;
elsif (rising_edge(clk)) then ...Quartus II synthesis generates the above warning and applies a high power-up value to the count_down register.
To avoid this warning, when declaring an integer signal, assign an initial value equal to the reset value. In the above example, the warning is not generated if the signal is declared with an inital value of 255:
signal count_down : integer range 0 to 255 := 255;For more information on register power-up values in Altera devices, see the Quartus II Handbook chapter Recommended HDL Coding Styles (PDF).