Article ID: 000087101 Content Type: Error Messages Last Reviewed: 06/09/2014

Warning (332056): PLL cross checking found inconsistent PLL clock settings

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may encounter the above warning when compiling the XAUI PHY IP using Quartus® II software version 13.1 for Arria® V, Cyclone® V, and Stratix® V transceiver devices. This is due to missing SDC constraints for the XAUI PHY IP clocks.
Resolution

To fix this problem, add the following SDC constraints for the XAUI PHY IP clocks before running the compilation:

create_clock -period <value> -name <clock_name> [get_ports pll_ref_clk]
create_clock -period <value> -name <clock_name> [get_ports phy_mgmt_clk]
derive_pll_clocks

Related Products

This article applies to 12 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.