Article ID: 000087073 Content Type: Troubleshooting Last Reviewed: 08/20/2018

Why does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Arria® V GZ FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Stratix® V Hard IP for PCI Express Intel® FPGA IP
  • Stratix® V Hard IP for PCI Express Intel® FPGA IP
  • IP_Compiler for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You might see timeout, rollover, and recovery because of Start of Packet(SOP) pointer buffer overflow. The SOP pointer buffer can overflow during replay because of internal error message or TLPs submitted from user side for transmission when the following trigger conditions are met:

    -     ACK packets are lost or not received by Intel® PCIe* Hard IP under a high bit error rate link conditions

    -     Link partner is unable to ACK packets at regular intervals as per the spec for unknown reasons


    If the above trigger conditions persists, then there are chances that internal SOP pointer buffer will reach the full condition. Every replay after this will cause overflow because of error message scheduling (Replay Timeout, Replay Num Rollover) or TLPs are submitted from user side for transmission.

    Resolution

    There is no workaround to this problem.

    This problem will not be fixed in a future release of the Intel® Quartus® Prime software.

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