RapidIO II MegaCore Function User Guide Incorrectly Indicates Receiving an IDLE2 or Change in Received CS Field Command Triggers an Interrupt

According to the RapidIO II MegaCore Function User Guide, if you set the Enable CMD changed interrupt bit in the LP-Serial Lane n Status 2 register (offsets 0x218, 0x238, 0x258, and 0x278), then if the IP core detects a change in the cmd value in the CS field in a RapidIO packet it receives, the IP core generates an interrupt.

Also according to the RapidIO II MegaCore Function User Guide, if you set the Enable IDLE2 Received interrupt bit in the LP-Serial Lane n Status 2 register, then if the IP core detects an IDLE2 symbol in a RapidIO packet it receives, the IP core generates an interrupt.

However, whether you set the corresponding interrupt enable bit or not, the IP core does not generate an interrupt for either of these two events.

This issue has no workaround. Ensure that you read the IDLE2 Received status from the IDLE2 received field of the LP-Serial Lane n Status 1 (Far End Lane n Status) register (offsets 0x214, 0x234, 0x254, and 0x274) and that you read the CMD Changed status from the CMD changed field of the LP-Serial Lane n Status 3 (Received CS Field Commands) register (offsets 0x21C, 0x23C, 0x25C, and 0x27C), without relying on an interrupt signal.

This issue is fixed in version 14.0 of the RapidIO II MegaCore Function User Guide.