Article ID: 000086932 Content Type: Troubleshooting Last Reviewed: 12/06/2024

Why doesn’t the MAX® 10 DDR2 mem_odt signal toggle during calibration in both the RTL simulation and in hardware operation?

Environment

    Intel® Quartus® Prime Lite Edition
    Intel® Quartus® Prime Standard Edition
    DDR2 SDRAM Controller with UniPHY Intel® FPGA IP
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Critical Issue

Description

Due to a problem with the MAX® 10 DDR2 IP, the mem_odt signal doesn’t toggle during calibration. Although this is incorrect behavior for the mem_odt signal during calibration, there is no functional impact to the DDR2 interface.

After calibration, the mem_odt signal toggles as expected during memory write transactions.

Resolution

 

This problem is scheduled to be fixed in the Quartus® Prime Standard version 19.1.

Related Products

This article applies to 1 products

Intel® MAX® 10 FPGAs

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