Article ID: 000086932 Content Type: Troubleshooting Last Reviewed: 11/14/2018

Why doesn’t the Intel® MAX® 10 DDR2 mem_odt signal toggle during calibration in both the RTL simulation and in hardware operation?

Environment

  • Intel® Quartus® Prime Lite Edition
  • Intel® Quartus® Prime Standard Edition
  • DDR2 SDRAM Controller with UniPHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Intel® MAX® 10 DDR2 IP, the mem_odt signal doesn’t toggle during calibration. Although this is incorrect behavior for the mem_odt signal during calibration, there is no functional impact to the DDR2 interface.

    After calibration, the mem_odt signal toggles as expected during memory write transactions.

    Resolution

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.