Article ID: 000086918 Content Type: Product Information & Documentation Last Reviewed: 08/04/2016

How can I enable the FPGA2SDRAM bridge on Cyclone V SOC and Arria V SOC devices?


  • Quartus® II Subscription Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition

    The HPS bridges can be enabled from the Preloader (SPL/MPL) or U-boot and in some cases from Linux.

    The FPGA2SDRAM bridge FPGA port configuration is contained in the FPGA logic and before the bridge is enabled, the SDRAM subsystem must be put into an idle state and the FPGA port configuration must be applied.


    • The SDRAM subsystem must be idle to avoid data loss on active transitions (HPS running from on-chip RAM, all peripherals disabled)
    • If a new FPGA image is loaded the FPGA port configuration must be re-applied if the FPGA2SDRAM port configuration has changed.


    Preloaders (SPL) and U-boot generated from SOC EDS 13.1 and later contain extra functionality and build in functions to safely enable the HPS bridges.



    To enable the HPS FPGA2SDRAM bridge from the Preloader or U-Boot follow the steps below:


    • The Preloader checks the status of the FPGA and will automatically enable bridges configured in the QSYS / BSP if the FPGA is configured.
    • The Preloader supports programing the FPGA before running automatic bridge enable tests and code



    • The bridge_enable_handoff command can be run from the U-boot command prompt to enable bridges.   
    • This function puts the HPS and SDRAM into a safe state before enabling all bridges after appropriate checks
    • "run bridge_enable_handoff"


    Steps for manually enabling the HPS FPGA2SDRAM bridges

    • The FPGA fabric must be programed
    • The HPS SDRAM must be put into an idle state (HPS running from on-chip RAM, all peripherals disabled)
    • The FPGA2SDRAM FPGA port configuration must be applied by setting the "applycfg" bit within the sdr.ctrlgrp.staticcfg register
    • The bridge can be enabled by writing to the bridge control register


    • If the FPGA is re-programed with an FPGA image using the same FPGA2SDRAM port configuration, FPGA port configuration does not need to be re-applied. 
    • First time enabling of the FPGA2SDRAM bridge within Linux is not supported as the SDRAM subsystem cannot be easily put into a guaranteed idle state.


    This information will be included in a future release of the Cyclone V HPS Technical Reference Manual.

    Related Products

    This article applies to 5 products

    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA



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