Article ID: 000086902 Content Type: Troubleshooting Last Reviewed: 11/09/2018

Are there any placement restrictions for the Intel® Stratix® 10 HPS EMIF IP PLL reference clock and RZQ pin ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces for HPS Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro software versions 19.1 and earlier, an Intel Stratix® 10 hard processor system (HPS) project may fail device configuration.  The project may incorrectly pass compilation  with an invalid pin placement of the HPS EMIF IP PLL reference clock and RZQ pin.

    Resolution

    In the Intel® Stratix® 10 HPS EMIF interface, the PLL reference clock and RZQ pin must be placed in IO bank 2M with the address and command signals. FPGA configuration will fail if this pinout restriction is not followed.

    This problem is fixed beginning with the Intel Quartus Prime Pro Edition software version 19.2, by reporting an error during compilation if the pin placement requirements are not followed. Refer to the External Memory Interfaces Intel Stratix 10 FPGA IP User Guide  for more information regarding the HPS EMIF pin placement restrictions.

    If you have a design that is currently passing FPGA device configuration in a release earlier than the Intel Quartus Prime Pro software version 19.2 which fails in compilation in Intel Quartus Prime Pro software version 19.2 and later, then you do not need to change the HPS EMIF design but will need a workaround.
    Contact Intel for further details.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA

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