Is there any problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices?

No, there is no problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices. Leakage can occur between VCC and VCCIO as well as between VCC and VCCPT, which can cause both VCCIO and VCCPT to float up to a maximum approximation of 0.8V before the power supply is ramped up and after the power supply is ramped down.

This is expected behavior, and if the power-up and power-down sequences are followed, it will neither cause any functional failure nor concern the device's reliability.

This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down.

This is an expected behavior and will neither cause any functional failure nor reliability concern to the device if the power-up sequence and power-down sequence are followed.

This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down.