Article ID: 000086809 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why are the strobe_out and strobe_out_n signals placed in non-adjacent pins when using the complementary strobe in the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
    PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP, the strobe_out and strobe_out_n signals are placed in non-adjacent pins when you select complementary strobes and compile the design without pin location assignments.

Resolution

To work around this problem, assign the pin locations of the strobe_out and strobe_out_n signals by placing them to the adjacent DQS/DQSn pins.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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