Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see this error message while simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example with the Cadence* Xcelium* simulator.
To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, follow the steps below:
- Go to <example_design_path>/sim/ed_sim/sim/xcelium/
- Open xcelium_setup.sh with your preferred text editor
- Locate 'USER_DEFINED_ELAB_OPTIONS' line and add the '-timescale 1ps/1ps' option. After editing xcelium_setup.sh, the 'USER_DEFINED_ELAB_OPTIONS' line will look as follows: USER_DEFINED_ELAB_OPTIONS="-timescale 1ps/1ps"
- Execute ./xcelium_setup.sh
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.