Description
The write data FIFO is referring to the “wr_mem” bus in the Serial Flash Mailbox Client IP core for Stratix® 10 FPGAs. To pre-store data into write data FIFO, you need to write data to the “wr_mem” bus. You may refer to the IP wr_mem’s base and end address in the Platform Designer for the start address and list of addresses that you can write into.
Resolution
For more details about the write operation flow, you may refer to the Serial Flash Mailbox Client IP Core User Guide for Stratix® 10 FPGAs.