Article ID: 000086747 Content Type: Product Information & Documentation Last Reviewed: 10/10/2018

How can data be pre-stored into the write data FIFO in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core with JTAG Master as Host?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Altera S10 Mailbox Client Core
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The write data FIFO is referring to the “wr_mem” bus in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core. To pre-store data into write data FIFO, you need to write data to the “wr_mem” bus. You may refer to the IP wr_mem’s base and end address in the Intel® Quartus® Prime Platform Designer for the start address and list of addresses that you can write into. 

     

    For more details about the write operation flow, you may refer to Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core User Guide.

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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