Article ID: 000086719 Content Type: Troubleshooting Last Reviewed: 11/14/2024

Why does the RTL Viewer shows 'The RTL netlist is not available. Run Analysis and Elaboration to view RTL netlist'?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When choosing the Aggressive Compile Time optimization mode in the Quartus® Prime Pro Edition Software version 19.1 or later, this message may be seen when opening the RTL Viewer after a successful compilation process. When selecting the Aggressive Compile Time optimization mode, the Quartus® Prime Pro Edition Software does not generate a full synthesis netlist to reduce the compilation time. Without a full synthesis netlist, the RTL Viewer cannot elaborate a browsable RTL diagram.

Resolution

To work around this problem, select a different optimization mode in the Quartus® Prime Pro Edition Software and recompile the design.

Related Products

This article applies to 3 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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