Article ID: 000086687 Content Type: Error Messages Last Reviewed: 03/17/2021

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PHYLITE_GROUP(s)).

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to the limitation of the PHY Lite for Parallel Interfaces Intel® FPGA IP, you may see the error message above if you have more than one PHY Lite for Parallel Interfaces Intel FPGA IP place in the same I/O bank.

Resolution

To work around this problem, avoid placing more than one PHY Lite for Parallel Interfaces Intel® FPGA IP place in the same I/O bank. This is because each of the PHY Lite for Parallel Interfaces Intel FPGA IP has a specific interface requirement which required a specific PLL setting. However, there is only one PLL available in a given bank.

Related Products

This article applies to 3 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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