Article ID: 000086670 Content Type: Troubleshooting Last Reviewed: 12/20/2022

Why do my data send to NOR Flash incorrect when I am using OPCODE command in the Intel® Stratix® 10 Serial Flash Mailbox Client IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Configuration Clock Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Intel® Stratix® 10 Serial Mailbox Client IP, you will observe incorrect data being sent to the flash when you are sending data using the WRITEDATA_0 and WRITEDATA_1 register. This is because the byte ordering is in little-endian format. This will be the same as performing read-data operation.

    Based on the SPI interface protocol, the most significant bit (MSB) is being sent or received when the data is transmitted. So each byte will be stored from the least significant bit (LSB) to the MSB of the READDATA_0, READDATA_1, WRITEDATA_0, and WRITEDATA_1. In other words, the data in the register will transmit the LSB byte to the MSB byte of the read or write data register.

    Resolution

    To resolve the problem, you will need to reverse the byte ordering of the 4 byte data on the WRITEDATA_0 or WRITEDATA_1 register

    For example- 4 byte of data "0x11223344" is actually "0x44332211".

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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