Article ID: 000086602 Content Type: Troubleshooting Last Reviewed: 06/24/2021

Why is the Configuration via Protocol (CvP) Initialization / CvP Update not functioning in Intel® Agilex™ F-Tile & R-Tile devices?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Agilex™ I-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.2, performing CvP Initialization / CvP Update with Intel® Agilex™ F-Tile & R-Tile devices is not functioning properly. This is because the PCIe link is not able to enumerate properly after the periphery image is being loaded.

    For Intel® Agilex™ F-Tile devices, the PCIe link can enumerate when loading the full image instead of periphery image. Performing CvP Update will pass after the CvP PCIe link is enumerated properly. Non CvP use case is not affected by this problem.

    For Intel® Agilex™ R-Tile devices, the PCIe link can enumerate when loading the full image instead of periphery image. However, performing CvP Update will fail. Non CvP use case is not affected by this problem. 

    Resolution

     

    For more information contact Intel Premier Support and quote ID 1509023430.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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