Article ID: 000086541 Content Type: Troubleshooting Last Reviewed: 12/18/2018

Why do I see unbalanced memory throughput between the 2 cpu cores in Cyclone® V SoC, Arria® V SoC and Arria® 10 SoC FPGAs?”


  • Quartus® II Subscription Edition
  • Arria® V Cyclone® V Hard Processor System Intel® FPGA IP

    Memory access throughput between Core 0 and Core 1 becomes unbalanced under the following conditions:

    • CPU0 and CPU1 are accessing the memory subsystem at the same time
    • The aggregate memory throughput requested by the two cores exceeds the memory subsystem capacity
    • The Acceleration Coherency Port (ACP) is not being used or is being used with low bandwidth traffic

    The Snoop Control Unit of the CPU subsystem arbitrates requests from its three masters – CPU0, CPU1, and ACP – based on a round robin algorithm. That ensures a fair distribution of the available memory bandwidth.

    However, when all the above conditions occur, the SCU master arbitration fairness is reduced, because unused ACP arbitration shares are reassigned to CPU0, resulting in CPU0 getting up to twice the memory bandwidth of CPU1.


    If a balanced memory throughput between core 0 and core 1 is needed, the application running on core 0 must be designed to prevent it from using more than 50% of the available memory bandwidth.

    This information is scheduled to be included in a future release of the Cyclone® V SoC, Arria® V SoC and Intel® Arria® 10 SoC FPGA Technical Reference Manuals.

    Related Products

    This article applies to 7 products

    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Intel® Arria® 10 GT FPGA
    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Intel® Arria® 10 SX SoC FPGA



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