Article ID: 000086525 Content Type: Troubleshooting Last Reviewed: 03/22/2017

Can I manually instantiate Qsys Translator IP in a Qsys system?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® FPGA Interconnect
    AXI Translator Intel® FPGA IP
    APB Translator Intel® FPGA IP
    Avalon-MM Slave Translator Intel® FPGA IP
    Avalon-MM Master Translator Intel® FPGA IP
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Description

Due to a problem in the Quartus® Prime software version 16.1 and earlier AXI, Avalon MM and APB Translator IPs are visible in the Quartus Prime software Qsys IP Catalog window under Qsys Interconnect / Memory-Mapped section.

Translator IPs should not be manually added to Qsys systems,  Qsys will add them automatically to generate system interconnect.  

Resolution

This problem is due to be fixed in a future version of the Quartus Prime software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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