Article ID: 000086381 Content Type: Troubleshooting Last Reviewed: 08/19/2021

Why do I see cache coherency problems between the HPS and FPGA on Intel Agilex SoC designs in Intel Quartus Prime Pro version 20.4 and earlier?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel© Quartus© Prime Pro software version 20.4 and earlier,  cache coherency errors may be seen on Intel Agilex™ SoC designs for transactions via the FPGA to SOC bridge. 

    Resolution

    A patch to work around this problem has been released for u-boot-socfpga and is available on https://github.com/altera-opensource/u-boot-socfpga
    starting with the following branches 

    https://github.com/altera-opensource/u-boot-socfpga

    V2020.10

    • HSD #14012926793: cache: ncore: Disable snoop filter
    • Commit date : March 31 2021
    • commit ID c79c23c6201819ca32b6739eff2e2b25e19f6624

    This patch is included in later branches.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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