Article ID: 000086252 Content Type: Troubleshooting Last Reviewed: 02/22/2018

Why does the LPM_ADD_SUB IP core generate incorrect results?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro edition software, you may get incorrect results in hardware when using the LPM_ADD_SUB IP core for Intel Stratix® 10 devices. The problem occurs only when a pipeline stage of greater than 1 is used. The simulation yields correct results.

     

    Resolution

    To work around the problem, use pipeline stage of 1 or 0.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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