Why does the Intel® Quartus® Prime Software Fitter fail to find an IP generated clock when reading an SDC file ?

During the Fitter state, you might  see warnings like "Warning (332174): Ignored filter at *.sdc(<line number>): <clock> could not be matched with a clock.", even though the clock is generated by an Intel® FPGA IP.

This is because all the files in the project are processed in the order they are listed in the .qsf.

If the .sdc file is listed before the IP file that generates the clock then the constraint will fail.

To avoid this problem, reorder the files in the Quartus Setting File (.qsf) so that the .sdc file is listed after the IP files.