Article ID: 000086148 Content Type: Troubleshooting Last Reviewed: 04/05/2022

Why does the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP fail in hardware when the VCO is running around 1066 MHz (with Interface frequency around 266/533/1066MHz)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you may see a data slip on the output path of up to 800 cycles when the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP VCO frequency is around 1066 MHz, (i.e. interface frequency around 266MHz, 533MHz or 1066MHz).

    This problem only affects Intel® Agilex™ devices and is PVT dependent so it may occur even after successful hardware testing.

    Resolution

    A patch is being created to fix this problem in the Intel® Quartus® Prime Pro Edition Software version 21.2

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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