Due to the Intel® Hyperflex™ FPGA architecture in the Intel® Stratix® 10 and Intel® Agilex™ series devices the threshold for shift register inference is increased meaning that RTL based shift registers which may have been inferred as shift registers in previous technologies may not be inferred in Intel Stratix 10 and Intel Agilex series devices. The reason for this threshold increase is to allow more registers to be retimed as hyper registers which improves design performance.
Intel® Stratix® 10 and Intel® Agilex™ series shift register inference criteria:
Default requirement:
The shift register must contain at least 69 registers in total (depth * width)
-Note that an additional stage of inference takes place after the early retimer stage to recover area for registers which have not been retimed into Hyper register locations.
With the following assignment in place the total number of required registers (depth * width) drops to 37:
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-Note that an additional stage of inference takes place after the early retimer stage to recover area for registers which have not been retimed into Hyper register locations.
With both of the following assignments in place the total number of required registers (depth * width) drops to 13:
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE=OFF
-Note that reducing the shift register inference threshold can negatively impact design performance as it reduces the number of registers available for Hyper Retiming.
