The channel spacing of a PLL is defined as the desired accuracy of the synthesized output frequency, as measured before the effect of the output divider.
This field is editable in the Altera® PLL megafunction when fractional mode is selected. The granularity of the spacing is a function of the Phase Frequency Detector (PFD) frequency (fPFD) and the Delta-Sigma-Modulator (DSM) resolution.
For example, for a 24-bit DSM fPLL, this channel spacing has a minimum value of fPFD/(2^24).
In terms of applying or using this feature, if for example you are going to synthesize a 300MHz output clock and need an accuracy of 100ppm or better, this would translate into a channel spacing requirement of 30KHz or smaller, which is what you would enter into the megafunction.
Note that, in fractional mode, there is a tradeoff between channel spacing and loop performance. The general guidance is to use the largest channel spacing that is acceptable for the application, this will give the best jitter performance and the fastest lock time for the loop.