Article ID: 000086112 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I instantiate mulitiple copies of the same memory block that have different initialization files, without using the MegaWizard Plug-In Manager multiple times?



You can do this by passing the initialization file name as a parameter to the MegaWizard®-generated file for each instance of the ROM or RAM in the top level design. To do so, use the following procedure to edit the wrapper file generated by the MegaWizard Plug-In Manager and instantiate the instances in your design. The following example uses Verilog HDL for a ROM memory block.

  1. Add the definition of the parameter init_file to the MegaWizard-generated wrapper file, as follows:

    parameter init_file = "";

  2. Modify the megafunction instantiation in the wrapper file to assign the new init_file parameter as the altsyncram_component.init_file parameter value, as follows. This change makes the MegaWizard-generated customized ROM module parameterizable, and allows the instantiation of the customized ROM to define the value of the initialization file. 

        altsyncram_component.init_file = init_file,

  3. Delete the existing value of the altsyncram_component.init_file parameter, if one exists in the wrapper file. The following is an example of the modified wrapper file:

    module my_rom (address, clock, q);
       input [2:0] address;
       input clock;
       output [7:0] q;

       parameter init_file = "";
       wire [7:0] sub_wire0;
       wire [7:0] q = sub_wire0[7:0];
       altsyncram altsyncram_component (
           altsyncram_component.init_file = init_file, ...

  4. For each ROM instance in the top-level design, set the init_file parameter to the desired initialization file name.

    The following example shows one instantiation of the my_rom module, where defparam is used to pass the .mif initialization file to the parameter init_file. The design can include many instantiations of this ROM, each using a different initialization file, by setting the defparam.

    module top_level_roms (addr, clk, q);
       output [7:0] q;
       input clk;
       input [2:0] addr;

       my_rom u1 (.address(addr),.clock(clk),.q(q));
          defparam u1.init_file = "rom_test.mif";

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Stratix® II FPGAs



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