Due to a problem in the Intel® Quartus® Prime Pro edition software, you may see this error in the fitter stage. This error occurs when a virtual pin assignment is set to the pll_ref_clk pin of the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP in an Intel® Stratix® 10 MX device.
The pll_ref_clk pin must be connected to the dedicated pin and a virtual pin assignment cannot be used for this pin.
To work around this problem, remove the virtual pin assignment from the pll_ref_clk pin of the HBM2 Interface Intel FPGA IP and connect it to a dedecated pll_ref_clk pin.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.