Article ID: 000086073 Content Type: Troubleshooting Last Reviewed: 03/06/2023

Why does my Intel Agilex® 7 FPGA tri-state GPIO pin fail in hardware?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1 and later, you may see that any tri-state GPIO pin on your Intel Agilex® 7 FPGA device does not function correctly in hardware. This is because the polarity of the output enable signal is incorrect.

    Resolution

    To work around this problem, invert the output enable signal in your RTL or download and install the following patch.

    This problem is fixed beginning with version 21.3 of the Intel® Quartus® Prime Pro Edition Software.

     

     

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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